1. Technical Field
The present teaching relates to analog circuits. Particularly, the present teaching relates to analog-to-digital converters (ADCs).
2. Discussion of Technical Background
Analog-to-digital converters (ADCs) are used for a wide range of applications, including, but not limited to, sensor interfaces, industrial applications, consumer applications, and communications. Various circuits and techniques have been developed for analog-to-digital (A/D) conversion targeting various applications and their varying requirements in terms of speed, resolution, noise, power consumption, and other performance related parameters.
Successive approximation is a well-known sequential method used for A/D conversion, where an analog signal value may be sampled on a capacitive digital-to-analog converter structure (CDAC), and a sequential successive-approximation process is used to generate a digital representation of the analog signal value. Each step of a successive-approximation A/D conversion process may determine one bit of the digital representation, e.g., it may take 16 steps to generate a digital representation of 16-bit resolution. Accordingly, a maximum conversion rate limit for a successive-approximation ADC may be relatively low, e.g., one mega-samples-per-second (1 MSPS).
Sequential residue amplification is a well-known method for A/D conversion used in a pipelined ADC. FIG. 1(a) (Prior Art) shows a pipelined ADC 100 comprising three residue-amplifying circuit stages 101, 102, and 103, that are commonly known as MDAC stages. A first MDAC stage 101 receives and samples an analog input signal value a1(k), and provides a first digital code d1 and an analog value a2 that is an amplified residue of a1(k) with respect to d1 and a reference voltage VREF. FIG. 1(b) shows an exemplary implementation of MDAC 101 comprising a sample-and-hold (S/H) stage 101-1, a flash ADC 101-2, a digital-to-analog converter (DAC) 101-3, and an amplifier circuit 101-4. Sample-and-hold stage 101-1 samples analog input signal a1 and provides sampled analog input signal value a1(k). Flash ADC 101-2 evaluates a1(k) and provides digital code d1 representing a1(k). For example, d1 may be a 2-bit representation of a1(k). DAC 101-3 receives digital code d1 and provides a voltage d1*VREF. Amplifier circuit 101-4 receives a1(k) and d1*VREF and provides an amplified residue voltage a2=A*(a1(k)−d1*VREF). Residue amplification factor A may, for example, be A=4. The output signals d1, a2 from MDAC 101 are delayed by one clock cycle with respect to the input signal a1. Such delays are not represented explicitly in FIGS. 2(a) and 2(b), which show (in part) nominal relationships of d1 and a2 with respect to a1 for a full-scale range of ADC 100 (from 0 Volts to VREF). MDAC stages 102 and 103 may be identical to the first MDAC stage 101. FIGS. 2(c)-2(f) show the input and output signals of these stages with respect to a1. A digital combiner circuit 104 combines the first, second, and third digital codes d1, d2, d3 generated by MDAC circuits 101, 102, and 103 to provide a digital representation d(k) of the sampled analog input signal value a1(k). Note that d(k) is delayed by 3 clock cycles with respect to a1. A 2-clock-cycle delay circuit 105 is used to align d1 with d3, and a 1-clock-cycle delay circuit 106 is used to align d2 with d3. The residue amplification factors implemented by MDAC circuits 101, 102, and 103 are taken into account by the digital combiner circuit 104, and a numerical value of d(k)=d1+d2/4+d3/16 may represent a ratio a1(k)/VREF.
A pipelined ADC may comprise more or fewer MDAC stages than ADC 100. In addition, each individual MDAC stage may resolve a different number of bits. For example, a 4-stage pipelined ADC may resolve 6+4+2+2 bits using 4 MDAC stages to provide a 14-bit digital representation of an analog input signal value. Each stage of a pipelined ADC may perform one step of an overall A/D conversion process (of a particular analog signal value), but all stages may operate at the same time (each stage operating on distinct analog signal values). A pipelined ADC may be designed to operate at a higher conversion rate than that of a successive-approximation ADC, in part because each stage may perform only a small portion of the overall A/D conversion process, and in part because the pipelined conversion process may comprise fewer steps than the successive-approximation conversion process.
The process of passing an analog signal from one MDAC stage to another in a pipelined ADC (for example, a2 in ADC 100 of FIG. 1(a)) may cause accumulation of errors and noise. For example, amplifier circuit 101-4 in MDAC 101 of FIG. 1(b) may have a limited bandwidth, and may settle gradually towards a nominal value of a2. Incomplete settling may cause settling errors. To reduce such errors, an MDAC stage of a pipelined ADC may be required to achieve a relatively high degree of accuracy, which may impose a limit on a maximum achievable conversion rate and/or accuracy. Successive-approximation ADCs may be more favorable in this regard, because an analog signal value may be represented as an amount of charge on a circuit node that is substantially isolated throughout the conversion process. By not moving the analog signal from one circuit stage to another, successive-approximation ADCs may be less prone to such errors.
Successive-approximation ADCs may be clocked (by a conversion control signal initiating an A/D conversion process for each analog signal value) periodically, in bursts, or only once in a while. The general-purpose nature of successive-approximation ADCs allow such converters to be used for a wide range of applications. Pipelined ADCs may potentially achieve a higher maximum conversion rate by processing several analog signal values simultaneously, but that may be advantageous primarily for applications that require a substantially periodical A/D conversion process.
A residue-amplifying A/D conversion process implemented by pipelined ADC 100 in FIG. 1(a) may alternatively be implemented based on a non-pipelined ADC wherein a single MDAC stage is used repeatedly. Such ADCs may be known as cyclic or algorithmic ADCs. FIG. 3 shows an algorithmic ADC 107 where the first MDAC stage 101 of ADC 100 is used repeatedly to generate three digital codes d1, d2, d3 that are combined by digital combiner circuit 104 to generate a 6-bit digital representation d(k) of an analog input signal value a1(k). In a first step of the conversion process, an analog multiplexer circuit 108 selects a1 to be processed by MDAC 101. MDAC 101 provides the first digital code d1 and an amplified residue signal r=a2 of a1(k) with respect to d1 and VREF. In a second step of the conversion process, the multiplexer 108 selects r=a2 to be processed by MDAC 101 providing the second digital code d2 and an amplified residue value r=a3 of a2 with respect to d2 and VREF. In a third step of the conversion process, the multiplexer 108 selects the residue r=a3 to be processed by MDAC 101 providing the third digital code d3, which is combined with the first and second digital codes to provide d(k). Algorithmic ADC 107 is similar to a successive-approximation ADC in that it operates on only one analog signal value at a time. ADC 107 may be modified so that MDAC 101 resolves more bits per step of the conversion process, and a high-resolution digital representation may be obtained in as few as 3 or 4 sequential steps. Accordingly, an algorithmic ADC may be designed to have a higher maximum conversion rate limit than that of a successive-approximation ADC. However, when an MDAC stage is required to achieve a high degree of accuracy, it may impose a limit on a maximum conversion rate and overall accuracy that may be achieved.
What is needed is a general-purpose ADC circuit that can operate at a high conversion rate and maintain a high degree of accuracy.